9. QP-nano Memory Usage

This QP-nano Tutorial is adapted from Chapter 1 of Practical UML Statecharts in C/C++, Second Edition
by Miro Samek, the founder and president of Quantum Leaps, LLC.

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To give you an idea of the QP-nano memory usage, Table 10-1 and 10-2 show the memory footprint of the QP-nano components for various settings of the configuration macros. The data for Table 10-1 has been obtained from the IAR compiler for MSP430 v4.10A (the KickStart edition), while data for Table 10-2 has been obtained from the IAR compiler for ARM Cortex-M3 v5.11 (also the KickStart edition). In both cases I have selected optimization level High/Size. The first column of Table 10-1 and 10-2 lists the configuration macros that are significant for the RAM or ROM usage in QP-nano. I have omitted the QF_ISR_NEST and QF_ISR_KEY_TYPE macros, as they have virtually no impact on the code or data sizes shown in the tables (even though, defining QF_ISR_KEY_TYPE increases somewhat the stack usage.) Both MSP430 and Cortex-M3 offer good code density and the IAR compiler generates fantastic machine code for these CPU architectures. (I've seen much worse results for older CPU architectures, such as 8051 or the PIC). Therefore, you should treat the data in Table 10-1 and 10-2 as minimum memory footprint of QP-nano rather than average results. The intent of Table 10-1 is primarily to give you a general idea for the relative cost of various options, rather than to provide you absolutely accurate measurements.

Note:

The Table 10-1 and 10-2 show only the memory used directly by the QP-nano components, but do not include the memory required by the application. In particular, you don't see the stack usage, or the RAM required by active objects and their event queues.

Table 10-1 QP-nano memory usage in bytes for various settings of the configuration parameters (MSP430/IAR compiler/optimization-High/Size)

Table 10-2 QP-nano memory usage in bytes for various settings of the configuration parameters (ARM Cortex-M3/IAR compiler/optimization-High/Size)

The various QP-nano configurations are listed in Table 10-1 and 10-2 separately for the non-preemptive "vanilla" kernel (configurations 1-6) and the preemptive QK-nano kernel (configurations 7-12). Within each group, the simpler configurations come before the more expensive ones. For example, the absolutely minimal configuration number 1 eliminates the HSM code (so only basic FSM support is provided), uses no event parameters, no time events, and up to 4 active objects. This minimal configuration is clearly very limited. However, the configuration number 4 is already quite reasonable. It still offers only non-hierarchical FSMs, but includes event parameter, time events, and up to 8 active objects, at the cost of less than 700 bytes of code space. By far, the most expensive feature (in terms of ROM) is the HSM support, which costs about 650 bytes (e.g., compare configurations number 4 and 5 or 10 and 11). On the other hand, the QK-nano preemptive kernel increases the ROM footprint only by 50-100 bytes compared to the "vanilla" kernel. Obviously, the true cost of QK-nano lies in the increased stack requirements, which Table 10-1 and 10-2 don't show.

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